1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated semiconductor devices, and, more particularly, to bond pad configurations for controlling interactions between semiconductor chips and carrier substrates during the chip/carrier joining process.
2. Description of the Related Art
In the manufacture of modern integrated circuits, it is usually necessary to provide electrical connections between the various semiconductor chips making up a microelectronic device. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wirebonding, tape automated bonding (TAB), flip-chip bonding, and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to carrier substrates, or to other chips, by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry. In flip-chip technology, solder balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip comprising a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package, each of which corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier substrate, are then electrically connected by “flipping” the semiconductor chip and bringing the solder balls into physical contact with the bond pads, and performing a “reflow” process so that each solder ball bonds to a corresponding bond pad. Typically, hundreds of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips, and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
In many processing applications, a semiconductor chip is bonded to a carrier substrate during a high temperature so-called Controlled Collapse Chip Connection (C4) solder bump reflow process. Typically, the substrate material is an organic laminate, which has a coefficient of thermal expansion (CTE) that may be on the order of 4-5 times greater than that of the semiconductor chip, which, in many cases, is made up primarily of silicon and silicon-based materials. Accordingly, due to the coefficient of thermal expansion mismatch between the chip and the substrate (i.e., silicon vs. organic laminate), the substrate will grow more than the chip when exposed to the reflow temperature, and as a consequence, stresses will be imposed on the chip/substrate package as the package cools and the solder bumps solidify. FIGS. 1a-1c, which schematically illustrate at least some of the possible effects that may occur on a chip package during this process, will now be described.
FIG. 1a schematically illustrates a chip package 100, which includes a carrier substrate 101 and a semiconductor chip 102. The semiconductor chip 102 typically comprises a plurality of solder bumps 103, which are formed above a metallization system 104 (see FIG. 1c) of the chip 102. During the chip packaging assembly process, the semiconductor chip 102 is inverted, or “flipped,” and brought into contact the carrier substrate 101, after which the chip package 100 of FIG. 1a is exposed to a solder bump reflow process 120 at a reflow temperature that exceeds the melting temperature of the solder bump material. Depending on the specific solder alloy used to form the solder bumps 103, the reflow temperature may be upwards of 200-265° C. During the reflow process 120, when the material of the solder bumps 103 is in a liquid phase, both the carrier substrate 101 and the semiconductor chip 102 are able to thermally “grow” in a substantially unrestrained manner, based on the respective coefficient of thermal expansion of each component. As such, both the carrier substrate 101 and the semiconductor chip 102 remain in an essentially flat, non-deformed condition, although each will grow by a different amount due to their different coefficients of thermal expansion.
FIG. 1b, on the other hand, schematically illustrates the chip package 100 during a cool-down phase, when a thermal interaction begins to take place between the carrier substrate 101 and the semiconductor chip 102. As the chip package 100 cools, the solder bumps 103 solidify and mechanically join the package substrate 101 to the semiconductor chip 102. As the chip package 100 continues to cool after solder bump 103 solidification, the CTE mismatch between the materials of the carrier substrate 101 and the semiconductor chip 102 cause the substrate 101 to shrink at a greater rate than the chip 102. Typically, this difference in thermal expansion/contraction is accommodated by a combination of out-of-plane deformation of both the carrier substrate 101 and the semiconductor chip 102, and some amount of shear deformation of the solder bumps 103. Other localized effects may occur in the semiconductor chip 102 in areas immediately surrounding the solder bumps 103, as illustrated in FIG. 1c and described below.
FIG. 1c schematically illustrates an area of the semiconductor chip 102 surrounding an individual solder bump 103A after cool-down of the chip package 100. For simplicity, the semiconductor chip 102 has been inverted compared to the chip packaging configurations illustrated in FIGS. 1a-1b, and the carrier substrate is not shown. Furthermore, only the uppermost metallization layers 104A, 104B and 104C of a metallization system 104 of the semiconductor chip 102 are shown in FIG. 1c, any metallization layers below layer 104C, device layers, or substrate layers of the chip 102 have not been depicted. The semiconductor chip 102 also includes a bond pad 105 formed in the last metallization layer 104A, a passivation layer 106 formed above the last metallization layer 104A, and a solder bump 103A formed above the bond pad 105. Additionally, as shown in FIG. 1c, the bond pad 105 is in contact with a contact structure 107 so as to facilitate the electrical connection of the solder bump 103A and the carrier substrate 101 (not shown in FIG. 1c) to an integrated circuit (not shown) of the semiconductor chip 102 formed in the device level (not shown) below the metallization system 104. For illustrative purposes only, the contact structure 107 may include, for example, a contact via 107B formed in the metallization layer 104B, a conductive line 107C and a contact via 107D in the metallization layer 104C, and the like, whereas other configurations may also be used.
During the cool-down phase, the out-of-plane deformation of the chip package 100 that is caused by the thermal interaction of the semiconductor chip 102 and the carrier substrate 101 will develop as a shear load 103S, a tensile load 103T, and bending moment 103M across the solder bump 103A. However, since the solder material is, in general, very robust, and typically has a strength that exceeds that of the materials that make up the semiconductor chip 102—and in particular, the metallization system 104—relatively little deformation energy will be absorbed by the solder bump 103A. Instead, the majority of the loads 103S, 103T and 103M will be translated through the bond pad 105 and into the metallization layers underlying the solder bump 103A, resulting in highly localized tensile stresses, such as a vertical or uplift tensile stress 104U, and a lateral or stretching tensile stress 104S. If these tensile stresses are high enough, a local delamination of one or more of the uppermost metallization layers may occur below the solder bump 103A. Typically, a metallization layer delamination will manifest as a crack 108, and will normally occur where the uplift tension is highest—i.e., near the edge 105E of the bond pad 105, as shown in FIG. 1c. In many cases, the crack 108 may only occur in a single metallization layer, such as the layer 104B shown in FIG. 1c, whereas in other cases, the crack 108 may propagate deeper into the underlying metallization system 104, from one metallization layer to another.
Delamination failures and cracks, such as the crack 108, that may occur in a metallization layer below a solder bump 103 are sometimes subject to premature failure, as the solder bump 103 may not make a good electrical connection to the contact structures below. However, since the delamination/crack defects described above do not occur until the chip packaging assembly stage of semiconductor chip manufacture, the defects will generally not be detected until a final quality inspection is performed. Typically, after the flip-chip operation is completed, the chip package 100 will be subjected to acoustic testing, such as C-mode acoustic microscopy (CSAM). Cracks 108 that may be present in the metallization system 104 of the semiconductor chip 102 below the solder bumps 103 will have a white appearance during the CSAM inspection process, and are therefore sometimes referred to as “white bumps,” “white spots,” or “ghost bumps.” White bump defects impose a costly downside to the overall chip manufacturing process, as they do not occur, and hence cannot be detected, until a significant material and manufacturing investment in the chip has already occurred.
Moreover, recent changes and advances in the types of materials used in sophisticated semiconductor devices have also had an impact on the frequency in which white bumps occur. For example, for many years, the materials used for forming solder balls used in flip-chip technology included any one of a variety of so-called tin/lead (Sn/Pb) solders. Typically, the alloys that were used for most Sn/Pb solders have a level of ductility that enabled the Sn/Pb solder bumps to deform under the loads induced during the cool-down phase of the solder bump reflow process, thereby absorbing some of the out-of-plane deformation energy discussed above. However, in recent years, industries have generally moved away from the use of Sn/Pb solders in most commercial applications, including semiconductor processing. Accordingly, lead-free soldering materials, such as Sn/Ag (tin-silver), Sn/Cu (tin-copper), Sn/Ag/Cu (tin-silver-copper, or SAC) solders, and the like, have been developed as substitute alloys for forming solder bumps on semiconductor chips. These lead-free substitute soldering materials generally have a higher material strength and lower ductility than most of the commonly-used Sn/Pb solders, and also typically require higher temperatures for reflow. As such, less deformation energy is absorbed by lead-free solder bumps, and a commensurately higher loading is imparted on the metallization system underlying the solder bumps, which subsequently increases the frequency of white bump occurrence.
Additionally, the development and use of dielectric materials having a dielectric constant (or k-value) of approximately 3.0 or lower—which are often referred to as “low-k dielectric materials”—has led to an increased incidence of white bumps. Typically, low-k dielectric materials have lower mechanical strength, mechanical modulus, and adhesion strength than do some of the more commonly used dielectric materials having higher k-values, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. As metallization systems utilize more metallization layers that are made up of low-k dielectric materials, there is a greater likelihood that the lower strength low-k materials will rupture when exposed to the loads that are imposed on the metallization layers underlying the solder bumps, thus leading to delaminations and cracks—i.e., white bump defects. In particular, cracks tend to occur, or at least initiate, in the low-k metallization layers that are closest to the upper surface of the a semiconductor chip—i.e., closest to the last metallization layer—as the deformation energy is greatest near the upper surface, and lessens in lower metallization levels. Furthermore, it appears that the type of white bump problems described above are even further exacerbated in metallization layers comprised of ultra-low-k (ULK) materials having k-values of approximately 2.7 or lower.
It should be noted that, while FIGS. 1a-1c describe typical white bump problems that may be associated with flip-chip packaging problems, the issues identified above are equally applicable to other chip package configurations, such as 3D-chips and the like. Accordingly, and in view of the foregoing, there is a need to implement new design strategies to address the manufacturing issues associated with white bumps that occur during typical chip packaging operations. The present disclosure relates to process device designs and methods that are directed to avoiding, or at least mitigating, the effects of one or more of the problems identified above.